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Did the IBM System/4 Pi computer have radiation-hardened versions for Skylab and Shuttle?
What computer and software is used by the Falcon 9?Did the Surveyor missions measure secondary radiation?Mars and the radiation problemsHow was it possible for the Apollo 11 to film and take pictures with such radiation?How does methane and LOX compare to water for radiation shieldingDid Apollo-11 have any radiation shielding?How did Apollo missions solve the cosmic radiation problem?Bits per core for the different versions of the Apollo guidance computer core rope memory?Did the Apollo missions use the Earth's magnetotail to lessen cosmic radiation?How did the Apollo guidance computer handle parity bit errors?
$begingroup$
Wikipedia's article on the IBM System/4 Pi says:
The IBM System/4 Pi is a family of avionics computers used, in various versions, on the F-15 Eagle fighter, E-3 Sentry, AWACS, Harpoon Missile, NASA's Skylab, MOL, and the Space Shuttle, as well as other aircraft. The name of the system refers to the number of steradians (4π) in a sphere. Development began in 1965, deliveries in 1967.
It descends from the approach used in the System/360 mainframe family of computers in that members of the family were intended for use in many varied user applications. Previously custom computers had been designed for each aerospace application, which was extremely costly.
It sounds like the idea of providing the System/4 Pi was to provide a bit of standardization, but spaceflight involves an elevated exposure to radiation.
Were there any aspects of the system that were further modified for radiation hardening in spaceflight applications, such as special chips or components or did the standard system already have sufficient hardening?
Source
radiation flight-computer computer
asked 4 hours ago
uhohuhoh
42.3k19162532
$endgroup$
add a comment |
$begingroup$
Wikipedia's article on the IBM System/4 Pi says:
The IBM System/4 Pi is a family of avionics computers used, in various versions, on the F-15 Eagle fighter, E-3 Sentry, AWACS, Harpoon Missile, NASA's Skylab, MOL, and the Space Shuttle, as well as other aircraft. The name of the system refers to the number of steradians (4π) in a sphere. Development began in 1965, deliveries in 1967.
It descends from the approach used in the System/360 mainframe family of computers in that members of the family were intended for use in many varied user applications. Previously custom computers had been designed for each aerospace application, which was extremely costly.
It sounds like the idea of providing the System/4 Pi was to provide a bit of standardization, but spaceflight involves an elevated exposure to radiation.
Were there any aspects of the system that were further modified for radiation hardening in spaceflight applications, such as special chips or components or did the standard system already have sufficient hardening?
Source
radiation flight-computer computer
asked 4 hours ago
uhohuhoh
42.3k19162532
$endgroup$
add a comment |
$begingroup$
Wikipedia's article on the IBM System/4 Pi says:
The IBM System/4 Pi is a family of avionics computers used, in various versions, on the F-15 Eagle fighter, E-3 Sentry, AWACS, Harpoon Missile, NASA's Skylab, MOL, and the Space Shuttle, as well as other aircraft. The name of the system refers to the number of steradians (4π) in a sphere. Development began in 1965, deliveries in 1967.
It descends from the approach used in the System/360 mainframe family of computers in that members of the family were intended for use in many varied user applications. Previously custom computers had been designed for each aerospace application, which was extremely costly.
It sounds like the idea of providing the System/4 Pi was to provide a bit of standardization, but spaceflight involves an elevated exposure to radiation.
Were there any aspects of the system that were further modified for radiation hardening in spaceflight applications, such as special chips or components or did the standard system already have sufficient hardening?
Source
radiation flight-computer computer
asked 4 hours ago
uhohuhoh
42.3k19162532
$endgroup$
Wikipedia's article on the IBM System/4 Pi says:
The IBM System/4 Pi is a family of avionics computers used, in various versions, on the F-15 Eagle fighter, E-3 Sentry, AWACS, Harpoon Missile, NASA's Skylab, MOL, and the Space Shuttle, as well as other aircraft. The name of the system refers to the number of steradians (4π) in a sphere. Development began in 1965, deliveries in 1967.
It descends from the approach used in the System/360 mainframe family of computers in that members of the family were intended for use in many varied user applications. Previously custom computers had been designed for each aerospace application, which was extremely costly.
It sounds like the idea of providing the System/4 Pi was to provide a bit of standardization, but spaceflight involves an elevated exposure to radiation.
Were there any aspects of the system that were further modified for radiation hardening in spaceflight applications, such as special chips or components or did the standard system already have sufficient hardening?
Source
radiation flight-computer computer
radiation flight-computer computer
asked 4 hours ago
uhohuhoh
42.3k19162532
asked 4 hours ago
uhohuhoh
42.3k19162532
asked 4 hours ago
uhohuhoh
42.3k19162532
asked 4 hours ago
uhohuhoh
42.3k19162532
asked 4 hours ago
uhohuhoh
42.3k19162532
42.3k19162532
add a comment |
add a comment |
1 Answer
1
active
oldest
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$begingroup$
The IBM AP-101S used as the flight computer on the Space Shuttle in the latter part of the program was known to ops personnel as the General Purpose Computer (GPC). Each of the 5 GPCs in the Data Processing System (DPS) had 256k (yes k) of CMOS memory.
This memory was volatile and prone to corruption by radiation (Single Event Upsets, SEUs). Thus there were additional bits of memory for each halfword used for Error Correcting Code (ECC), parity checking, and code overwrite protection. A separate microprocessor performed the error checking.
Only the main memory was protected by ECC, CPU registers were not.
The original shuttle GPC, the AP-101B, had non-volatile memory, but the S model was half the size and had greatly reduced power and cooling loads.
Source:
Sadly, personal notes. There is an old Shuttle DPS Overview Training manual available online here but this info likely came from the more detailed HW/SW training manual which I did not find online (but it may be available from Wichita State University or Texas Tech)
answered 3 hours ago
Organic MarbleOrganic Marble
62.6k4169264
$endgroup$
1
$begingroup$
Wow thank you for the great and well backgrounded answer. It's great that you have and are such a deep library of information! Do you happen to know what kind of memory the non-volatile memory was? For example, was it SRAM, or FLASH, or magnetic Bubble memory, or something else?
$endgroup$
– uhoh
2 hours ago
1
$begingroup$
I saw a bunch of GPCs in the Shuttle Avionics Integration Lab for the first time about a week ago. I hadn't realized SAIL is a location on the JSC tour, but it is! One of the only actual-size shuttle cockpits that I've seen (instead of overlarge ones for simulators).
$endgroup$
– Erin Anne
38 mins ago
add a comment |
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1 Answer
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$begingroup$
The IBM AP-101S used as the flight computer on the Space Shuttle in the latter part of the program was known to ops personnel as the General Purpose Computer (GPC). Each of the 5 GPCs in the Data Processing System (DPS) had 256k (yes k) of CMOS memory.
This memory was volatile and prone to corruption by radiation (Single Event Upsets, SEUs). Thus there were additional bits of memory for each halfword used for Error Correcting Code (ECC), parity checking, and code overwrite protection. A separate microprocessor performed the error checking.
Only the main memory was protected by ECC, CPU registers were not.
The original shuttle GPC, the AP-101B, had non-volatile memory, but the S model was half the size and had greatly reduced power and cooling loads.
Source:
Sadly, personal notes. There is an old Shuttle DPS Overview Training manual available online here but this info likely came from the more detailed HW/SW training manual which I did not find online (but it may be available from Wichita State University or Texas Tech)
answered 3 hours ago
Organic MarbleOrganic Marble
62.6k4169264
$endgroup$
1
$begingroup$
Wow thank you for the great and well backgrounded answer. It's great that you have and are such a deep library of information! Do you happen to know what kind of memory the non-volatile memory was? For example, was it SRAM, or FLASH, or magnetic Bubble memory, or something else?
$endgroup$
– uhoh
2 hours ago
1
$begingroup$
I saw a bunch of GPCs in the Shuttle Avionics Integration Lab for the first time about a week ago. I hadn't realized SAIL is a location on the JSC tour, but it is! One of the only actual-size shuttle cockpits that I've seen (instead of overlarge ones for simulators).
$endgroup$
– Erin Anne
38 mins ago
add a comment |
$begingroup$
The IBM AP-101S used as the flight computer on the Space Shuttle in the latter part of the program was known to ops personnel as the General Purpose Computer (GPC). Each of the 5 GPCs in the Data Processing System (DPS) had 256k (yes k) of CMOS memory.
This memory was volatile and prone to corruption by radiation (Single Event Upsets, SEUs). Thus there were additional bits of memory for each halfword used for Error Correcting Code (ECC), parity checking, and code overwrite protection. A separate microprocessor performed the error checking.
Only the main memory was protected by ECC, CPU registers were not.
The original shuttle GPC, the AP-101B, had non-volatile memory, but the S model was half the size and had greatly reduced power and cooling loads.
Source:
Sadly, personal notes. There is an old Shuttle DPS Overview Training manual available online here but this info likely came from the more detailed HW/SW training manual which I did not find online (but it may be available from Wichita State University or Texas Tech)
answered 3 hours ago
Organic MarbleOrganic Marble
62.6k4169264
$endgroup$
1
$begingroup$
Wow thank you for the great and well backgrounded answer. It's great that you have and are such a deep library of information! Do you happen to know what kind of memory the non-volatile memory was? For example, was it SRAM, or FLASH, or magnetic Bubble memory, or something else?
$endgroup$
– uhoh
2 hours ago
1
$begingroup$
I saw a bunch of GPCs in the Shuttle Avionics Integration Lab for the first time about a week ago. I hadn't realized SAIL is a location on the JSC tour, but it is! One of the only actual-size shuttle cockpits that I've seen (instead of overlarge ones for simulators).
$endgroup$
– Erin Anne
38 mins ago
add a comment |
$begingroup$
The IBM AP-101S used as the flight computer on the Space Shuttle in the latter part of the program was known to ops personnel as the General Purpose Computer (GPC). Each of the 5 GPCs in the Data Processing System (DPS) had 256k (yes k) of CMOS memory.
This memory was volatile and prone to corruption by radiation (Single Event Upsets, SEUs). Thus there were additional bits of memory for each halfword used for Error Correcting Code (ECC), parity checking, and code overwrite protection. A separate microprocessor performed the error checking.
Only the main memory was protected by ECC, CPU registers were not.
The original shuttle GPC, the AP-101B, had non-volatile memory, but the S model was half the size and had greatly reduced power and cooling loads.
Source:
Sadly, personal notes. There is an old Shuttle DPS Overview Training manual available online here but this info likely came from the more detailed HW/SW training manual which I did not find online (but it may be available from Wichita State University or Texas Tech)
answered 3 hours ago
Organic MarbleOrganic Marble
62.6k4169264
$endgroup$
The IBM AP-101S used as the flight computer on the Space Shuttle in the latter part of the program was known to ops personnel as the General Purpose Computer (GPC). Each of the 5 GPCs in the Data Processing System (DPS) had 256k (yes k) of CMOS memory.
This memory was volatile and prone to corruption by radiation (Single Event Upsets, SEUs). Thus there were additional bits of memory for each halfword used for Error Correcting Code (ECC), parity checking, and code overwrite protection. A separate microprocessor performed the error checking.
Only the main memory was protected by ECC, CPU registers were not.
The original shuttle GPC, the AP-101B, had non-volatile memory, but the S model was half the size and had greatly reduced power and cooling loads.
Source:
Sadly, personal notes. There is an old Shuttle DPS Overview Training manual available online here but this info likely came from the more detailed HW/SW training manual which I did not find online (but it may be available from Wichita State University or Texas Tech)
answered 3 hours ago
Organic MarbleOrganic Marble
62.6k4169264
answered 3 hours ago
Organic MarbleOrganic Marble
62.6k4169264
answered 3 hours ago
Organic MarbleOrganic Marble
62.6k4169264
answered 3 hours ago
Organic MarbleOrganic Marble
62.6k4169264
62.6k4169264
1
$begingroup$
Wow thank you for the great and well backgrounded answer. It's great that you have and are such a deep library of information! Do you happen to know what kind of memory the non-volatile memory was? For example, was it SRAM, or FLASH, or magnetic Bubble memory, or something else?
$endgroup$
– uhoh
2 hours ago
1
$begingroup$
I saw a bunch of GPCs in the Shuttle Avionics Integration Lab for the first time about a week ago. I hadn't realized SAIL is a location on the JSC tour, but it is! One of the only actual-size shuttle cockpits that I've seen (instead of overlarge ones for simulators).
$endgroup$
– Erin Anne
38 mins ago
add a comment |
1
$begingroup$
Wow thank you for the great and well backgrounded answer. It's great that you have and are such a deep library of information! Do you happen to know what kind of memory the non-volatile memory was? For example, was it SRAM, or FLASH, or magnetic Bubble memory, or something else?
$endgroup$
– uhoh
2 hours ago
1
$begingroup$
I saw a bunch of GPCs in the Shuttle Avionics Integration Lab for the first time about a week ago. I hadn't realized SAIL is a location on the JSC tour, but it is! One of the only actual-size shuttle cockpits that I've seen (instead of overlarge ones for simulators).
$endgroup$
– Erin Anne
38 mins ago
1
1
$begingroup$
Wow thank you for the great and well backgrounded answer. It's great that you have and are such a deep library of information! Do you happen to know what kind of memory the non-volatile memory was? For example, was it SRAM, or FLASH, or magnetic Bubble memory, or something else?
$endgroup$
– uhoh
2 hours ago
$begingroup$
Wow thank you for the great and well backgrounded answer. It's great that you have and are such a deep library of information! Do you happen to know what kind of memory the non-volatile memory was? For example, was it SRAM, or FLASH, or magnetic Bubble memory, or something else?
$endgroup$
– uhoh
2 hours ago
1
1
$begingroup$
I saw a bunch of GPCs in the Shuttle Avionics Integration Lab for the first time about a week ago. I hadn't realized SAIL is a location on the JSC tour, but it is! One of the only actual-size shuttle cockpits that I've seen (instead of overlarge ones for simulators).
$endgroup$
– Erin Anne
38 mins ago
$begingroup$
I saw a bunch of GPCs in the Shuttle Avionics Integration Lab for the first time about a week ago. I hadn't realized SAIL is a location on the JSC tour, but it is! One of the only actual-size shuttle cockpits that I've seen (instead of overlarge ones for simulators).
$endgroup$
– Erin Anne
38 mins ago
add a comment |
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