Etydhv

The following answers mention the use of parity bits in the Apollo guidance computer:

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  this answer to Bits per core for the different versions of the Apollo guidance computer core rope memory?
  


• 
  this answer to How did the Apollo computers evaluate transcendental functions like sine, arctangent, log?
  

This leads me to wonder:

1. How did the Apollo guidance computer handle parity bit errors?


2. Were these ever encountered during actual missions?

What a fascinatingly obscure question :-) It took some digging, so perhaps someone who's actually seen an AGC might know better:

The parity bit was used to verify that data transferred correctly from memory to the registers. That is, the data in the memory was assumed to be correct, and the error was assumed to take place between the electronics that transfer from the core memory to the registers.

If a parity bit error were detected, then a parity alarm would happen. This actually was displayed on the DSKY and caused a restart of the programs currently running. It was so important that a parity circuit existed in the AGC. It was one of many hardware failure detection systems that protected the AGC during such failures. You can read a lot more about the restart system here here, which describes the parity stuff.

I cannot find any reference to a parity alarm ever occurring, but I haven't looked too hard at the moment. I expect it would be in the mission communications logs if it did.

1. How did the Apollo guidance computer handle parity bit errors?

According to Apollo 15 Hardware by Delco Electronics,

Parity Alarm

Occurs if any accessed word in fixed or erasable memory whose address is $10_8$ or greater contains an even number of "ones." All locations of $10_8$ or greater are stored in fixed or erasable memory with odd parity.

$10_8$ is octal 10 or decimal 8.

This condition triggers an automatic hardware restart:

A RESTART (hardware) and subsequent AGC/LGC Warning is generated for the following alarms:

• Oscillator Failure


• Transfer Control (TC) Trap


• Parity Alarm


• Nightwatchman Fail


• Interrupt (RUPT) Lock


• Voltage Fail

The RESTART inhibits access to memory temporarily, freezes the computer, stores in process information and then transfers control to address 4000. This address has the information address for the next instruction after a RESTART that the software programmer has provided.

2. Were these ever encountered during actual missions?

According to the Apollo Program Summary Report, the most severe anomaly in the entire GN&C system was a transient voltage which gave an erroneous indication to the computer that the inertial attitude reference had been lost. It also states that an open gimbal rate feedback circuit caused unexpected oscillation of the redundant engine gimbal actuator assembly. However, of the computer itself, it unambiguously states:

The performance of the computer was flawless.

I would interpret that as no parity errors.